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XDLP472NE0FYW

Texas Instruments Incorporated

XDLP472NE0FYW 产品规格书
Texas Instruments Incorporated XDLP472NE0FYW
  • ECCN
    3A001.a.3
  • ECCN Governance
    EAR
  • HTS Code
    8542.31.00.30
  • SB Code
    8542.31.00.30
  • Technology
    CMOS
  • Width (mm)
    22.3
  • Length (mm)
    32.2
  • JESD-30 Code
    R-CPGA-P149
  • Package Code
    SPGA
  • Package Shape
    RECTANGULAR
  • Package Style
    GRID ARRAY, SHRINK PITCH Meter
  • Surface Mount
    NO
  • Terminal Form
    PIN/PEG
  • Address Bus Width
    0
  • Bus Compatibility
    I2C, SPI, USB
  • Terminal Position
    PERPENDICULAR
  • Number of Terminals
    149
  • Terminal Pitch (mm)
    1.27
  • Display Configuration
    1920 X 1080 PIXELS
  • Package Body Material
    CERAMIC, METAL-SEALED COFIRED
  • Seated Height-Max (mm)
    3.837
  • Supply Voltage-Max (V)
    1.95
  • Supply Voltage-Min (V)
    1.71
  • Supply Voltage-Nom (V)
    1.8
  • External Data Bus Width
    0
  • Supply Current-Max (mA)
    1200
  • Package Equivalence Code
    HPGA149,16X20,50
  • Clock Frequency-Max (MHz)
    130
  • uPs/uCs/Peripheral ICs Type
    DISPLAY CONTROLLER, DLP
  • Operating Temperature-Max (Cel)
    70
  • Operating Temperature-Min (Cel)
    0

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