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MN103SD0N

Panasonic Corporation

Panasonic Corporation MN103SD0N
  • ECCN
    3A991.a.2
  • ECCN Governance
    EAR
  • HTS Code
    8542.31.00.25
  • SB Code
    8542.31.00.25
  • Bit Size
    32
  • Technology
    CMOS
  • Width (mm)
    11
  • Length (mm)
    11
  • Speed (MHz)
    60
  • ADC Channels
    YES
  • DAC Channels
    NO
  • DMA Channels
    YES
  • JESD-30 Code
    S-PBGA-B257
  • PWM Channels
    YES
  • Package Code
    FBGA
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY, FINE PITCH Meter
  • Surface Mount
    YES
  • Terminal Form
    BALL
  • Address Bus Width
    0
  • DLA Qualification
    Not Qualified
  • Terminal Position
    BOTTOM
  • Number of I/O Lines
    195
  • Number of Terminals
    257
  • Program Memory Type
    MROM
  • Terminal Pitch (mm)
    0.5
  • Data RAM Size (bytes)
    32768
  • Package Body Material
    PLASTIC/EPOXY
  • Supply Voltage-Max (V)
    1.95
  • Supply Voltage-Min (V)
    1.65
  • Supply Voltage-Nom (V)
    1.8
  • External Data Bus Width
    0
  • Supply Current-Max (mA)
    100
  • Package Equivalence Code
    BGA(UNSPEC)
  • Clock Frequency-Max (MHz)
    60
  • Program Memory Size (words)
    786432
  • Program Memory Width (bits)
    8
  • uPs/uCs/Peripheral ICs Type
    MICROCONTROLLER
  • Peak Reflow Temperature (Cel)
    NOT SPECIFIED
  • Time@Peak Reflow Temperature-Max (s)
    NOT SPECIFIED

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MN103SD0N