Renesas Electronics Corp. ICS97ULP877BHLF | 搜芯易Sourcengine

Renesas Electronics Corp. ICS97ULP877BHLF

生命周期状态
Discontinued
RoHS
符合RoHS标准
REACH
REACH compliant
说明
PLL Based Clock Driver, 97ULP Series, 10 True Output(s), 0 Inverted Output(s), PBGA52
类别
Semiconductors Logic ICs Clock Drivers PLL BASED CLOCK DRIVER

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Width
4.5 mm
Family
97ULP
Length
7 mm
fmax-Min
350 MHz
JESD-30 Code
R-PBGA-B52
Package Code
VFBGA
JESD-609 Code
e3
Logic IC Type
PLL BASED CLOCK DRIVER
Package Shape
RECTANGULAR
Package Style
GRID ARRAY, VERY THIN PROFILE, FINE PITCH Meter
Surface Mount
YES
Terminal Form
BALL
Terminal Pitch
0.65 mm
Terminal Finish
MATTE TIN
Seated Height-Max
1 mm
Temperature Grade
COMMERCIAL
Terminal Position
BOTTOM
Input Conditioning
DIFFERENTIAL
Number of Functions
1
Number of Terminals
52
Qualification Status
Not Qualified
Package Body Material
PLASTIC/EPOXY
Number of True Outputs
10
Output Characteristics
3-STATE
Operating Temperature-Max
70 Cel
Operating Temperature-Min
0 Cel
Supply Voltage-Max (Vsup)
1.9 V
Supply Voltage-Min (Vsup)
1.7 V
Supply Voltage-Nom (Vsup)
1.8 V
Number of Inverted Outputs
0
Same Edge Skew-Max (tskwd)
0.04 ns