Maxim Integrated DS1004M | 搜芯易Sourcengine

Maxim Integrated DS1004M

生命周期状态
Discontinued
REACH
REACH compliant
说明
Silicon Delay Line, 1-Func, 5-Tap, CMOS, PDIP8
类别
Semiconductors Logic ICs Delay Lines SILICON DELAY LINE

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Width
7.62 mm
Family
1000
Length
9.375 mm
Technology
CMOS
JESD-30 Code
R-PDIP-T8
Package Code
DIP
JESD-609 Code
e0
Logic IC Type
SILICON DELAY LINE
Package Shape
RECTANGULAR
Package Style
IN-LINE Meter
Surface Mount
NO
Terminal Form
THROUGH-HOLE
Terminal Pitch
2.54 mm
Terminal Finish
TIN LEAD
Seated Height-Max
4.572 mm
Terminal Position
DUAL
Number of Functions
1
Number of Terminals
8
Number of Taps/Steps
5
Qualification Status
Not Qualified
Package Body Material
PLASTIC/EPOXY
Programmable Delay Line
NO
Supply Voltage-Nom (Vsup)
5 V