CY7C346B-25RI
Cypress Semiconductor Corporation
- 生命周期状态Discontinued
- REACHREACH compliant
- 说明UV PLD, 40ns, 128-Cell, CMOS, CPGA100
- 类别
- HTS Code8542.39.00.01
- SB Code8542.31.00.55
- JTAG BSTNO
- TechnologyCMOS
- Width (mm)33.3375
- Length (mm)33.3375
- JESD-30 CodeS-CPGA-P100
- Organization19 DEDICATED INPUTS, 64 I/O
- Package CodeWPGA
- Package ShapeSQUARE
- Package StyleGRID ARRAY, WINDOW Meter
- Surface MountNO
- Terminal FormPIN/PEG
- Output FunctionMACROCELL
- DLA QualificationNot Qualified
- Temperature GradeINDUSTRIAL
- Terminal PositionPERPENDICULAR
- Additional FeatureLABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
- Number of I/O Lines64
- Number of Terminals100
- Terminal Pitch (mm)2.54
- Number of Macro Cells128
- Package Body MaterialCERAMIC, METAL-SEALED COFIRED
- In-System ProgrammableNO
- Propagation Delay (ns)40
- Seated Height-Max (mm)5.715
- Supply Voltage-Max (V)5.5
- Supply Voltage-Min (V)4.5
- Supply Voltage-Nom (V)5
- Programmable Logic TypeUV PLD
- Package Equivalence CodePGA100M,13X13
- Clock Frequency-Max (MHz)62.5
- Number of Dedicated Inputs19
- Operating Temperature-Max (Cel)85
- Operating Temperature-Min (Cel)-40
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CY7C346B-25RI