Renesas Electronics Corp. 97ULP844AYHLF-T | 搜芯易Sourcengine

Renesas Electronics Corp. 97ULP844AYHLF-T

生命周期状态
Active
RoHS
符合RoHS标准
REACH
REACH compliant
说明
PLL Based Clock Driver
类别
Semiconductors Logic ICs Clock Drivers PLL BASED CLOCK DRIVER

HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Family
97ULP
Width (mm)
4
Length (mm)
4.5
JESD-30 Code
R-PBGA-B28
Package Code
VFBGA
Logic IC Type
PLL BASED CLOCK DRIVER
Package Shape
RECTANGULAR
Package Style
GRID ARRAY, VERY THIN PROFILE, FINE PITCH Meter
Surface Mount
YES
Terminal Form
BALL
Packing Method
TR
fmax-Min (MHz)
95
Terminal Position
BOTTOM
Input Conditioning
DIFFERENTIAL MUX
Number of Functions
1
Number of Terminals
28
Terminal Pitch (mm)
0.65
Package Body Material
PLASTIC/EPOXY
Number of True Outputs
4
Output Characteristics
3-STATE
Seated Height-Max (mm)
1
Supply Voltage-Max (V)
1.9
Supply Voltage-Min (V)
1.7
Supply Voltage-Nom (V)
1.8
Supply Current-Max (mA)
0.5
Package Equivalence Code
BGA28,5X6,25
Number of Inverted Outputs
0
Output Low Current-Max (mA)
9
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0
Same Edge Clock Skew Delay-Max (ns)
0.04