Renesas Electronics Corp. 91305AGILF | 搜芯易Sourcengine

Renesas Electronics Corp. 91305AGILF

生命周期状态
EOL
RoHS
符合RoHS标准
REACH
REACH compliant
说明
High Performance Communication Buffer TSSOP 3.10x4.40x1.00 mm 0.65mm Pitch
类别
Semiconductors Logic ICs Clock Drivers PLL BASED CLOCK DRIVER

HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Family
91305
Width (mm)
3
Length (mm)
4.4
JESD-30 Code
R-PDSO-G8
Package Code
TSSOP
Logic IC Type
PLL BASED CLOCK DRIVER
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
Packing Method
TUBE
fmax-Min (MHz)
133
Terminal Position
DUAL
Input Conditioning
STANDARD
Number of Functions
1
Number of Terminals
8
Terminal Pitch (mm)
0.65
Package Body Material
PLASTIC/EPOXY
Number of True Outputs
4
Seated Height-Max (mm)
1.2
Supply Voltage-Max (V)
3.63
Supply Voltage-Min (V)
2.97
Supply Voltage-Nom (V)
3.3
Supply Current-Max (mA)
80
Package Equivalence Code
TSSOP8,.25
Number of Inverted Outputs
0
Output Low Current-Max (mA)
12
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
-40
Same Edge Clock Skew Delay-Max (ns)
0.25