5962-8946802XC
Cypress Semiconductor Corporation
- 生命周期状态Discontinued
- 说明UV PLD, 60ns, 128-Cell, CMOS, CPGA68
- 类别
- ECCN3A001.a.2.c
- ECCN GovernanceEAR
- HTS Code8542.31.00.55
- SB Code8542.31.00.55
- JTAG BSTNO
- TechnologyCMOS
- Width (mm)27.9527
- Length (mm)27.9527
- JESD-30 CodeS-CPGA-P68
- Organization7 DEDICATED INPUTS, 52 I/O
- Package CodePGA
- Package ShapeSQUARE
- Package StyleGRID ARRAY Meter
- Surface MountNO
- Terminal FormPIN/PEG
- J-STD-609 Codee4
- Output FunctionMACROCELL
- Terminal FinishGOLD
- DLA QualificationNot Qualified
- Temperature GradeMILITARY
- Terminal PositionPERPENDICULAR
- Additional FeatureLABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
- Number of I/O Lines52
- Number of Terminals68
- Terminal Pitch (mm)2.54
- Number of Macro Cells128
- Package Body MaterialCERAMIC, METAL-SEALED COFIRED
- In-System ProgrammableNO
- Propagation Delay (ns)60
- Seated Height-Max (mm)5.08
- Supply Voltage-Max (V)5.5
- Supply Voltage-Min (V)4.5
- Supply Voltage-Nom (V)5
- Programmable Logic TypeUV PLD
- Package Equivalence CodePGA68,11X11
- Clock Frequency-Max (MHz)27.7
- Number of Dedicated Inputs7
- Operating Temperature-Max (Cel)125
- Operating Temperature-Min (Cel)-55
- Screening Level / Reference StandardMIL-STD-883
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