Xilinx,Inc. XCR3256XL-12CS280I | 搜芯易Sourcengine

Xilinx,Inc. XCR3256XL-12CS280I

生命周期状态
Transferred
说明
EE PLD, 12ns, 256-Cell, CMOS, PBGA280
类别
Semiconductors Programmable Logic ICs Programmable Logic Devices EE PLD

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.39.00.01
SB Code
8542.39.00.00

JTAG BST
YES
Technology
CMOS
Width (mm)
16
Length (mm)
16
JESD-30 Code
S-PBGA-B280
Organization
0 DEDICATED INPUTS, 164 I/O
Package Code
TFBGA
Package Shape
SQUARE
Package Style
GRID ARRAY, THIN PROFILE, FINE PITCH Meter
Surface Mount
YES
Terminal Form
BALL
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
DLA Qualification
Not Qualified
Temperature Grade
INDUSTRIAL
Terminal Position
BOTTOM
Additional Feature
YES
Number of I/O Lines
164
Number of Terminals
280
Terminal Pitch (mm)
0.8
Number of Macro Cells
256
Package Body Material
PLASTIC/EPOXY
In-System Programmable
YES
Propagation Delay (ns)
12
Seated Height-Max (mm)
1.2
Supply Voltage-Max (V)
3.6
Supply Voltage-Min (V)
2.7
Supply Voltage-Nom (V)
3.3
Programmable Logic Type
EE PLD
Package Equivalence Code
BGA280,19X19,32
Clock Frequency-Max (MHz)
88
Moisture Sensitivity Level
3
Number of Dedicated Inputs
0
Peak Reflow Temperature (Cel)
240
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
-40
Time@Peak Reflow Temperature-Max (s)
30