XC95288XV-7FG256C
Xilinx,Inc.
- 生命周期状态Discontinued
- 说明CPLD XC9500 Family 6.4K Gates 288 Macro Cells 125MHz 2.5V 256-Pin FBGA
- 类别
- HTS Code8542.39.00.01
- SB Code8542.31.00.55
- JTAG BSTYES
- TechnologyCMOS
- Width (mm)17
- Length (mm)17
- JESD-30 CodeS-PBGA-B256
- Organization0 DEDICATED INPUTS, 192 I/O
- Package CodeBGA
- Package ShapeSQUARE
- Package StyleGRID ARRAY Meter
- Surface MountYES
- Terminal FormBALL
- J-STD-609 Codee0
- Output FunctionMACROCELL
- Terminal FinishTin/Lead (Sn63Pb37)
- Number of Inputs192
- DLA QualificationNot Qualified
- Number of Outputs192
- Temperature GradeCOMMERCIAL
- Terminal PositionBOTTOM
- Additional FeatureYES
- Number of I/O Lines192
- Number of Terminals256
- Terminal Pitch (mm)1
- Number of Macro Cells288
- Package Body MaterialPLASTIC/EPOXY
- In-System ProgrammableYES
- Propagation Delay (ns)7.5
- Seated Height-Max (mm)2
- Supply Voltage-Max (V)2.62
- Supply Voltage-Min (V)2.37
- Supply Voltage-Nom (V)2.5
- Programmable Logic TypeFLASH PLD
- Package Equivalence CodeBGA256,16X16,40
- Clock Frequency-Max (MHz)125
- Moisture Sensitivity Level3
- Number of Dedicated Inputs0
- Peak Reflow Temperature (Cel)225
- Operating Temperature-Max (Cel)70
- Operating Temperature-Min (Cel)0
- Time@Peak Reflow Temperature-Max (s)30
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XC95288XV-7FG256C