XC73108-20PG144M
Xilinx,Inc.
- 生命周期状态Discontinued
- 说明UV PLD, 45ns, 108-Cell, CMOS, CPGA144
- 类别
- ECCN3A001.a.2.c
- ECCN GovernanceEAR
- HTS Code8542.31.00.55
- SB Code8542.31.00.55
- JTAG BSTNO
- TechnologyCMOS
- Width (mm)39.624
- Length (mm)39.624
- JESD-30 CodeS-CPGA-P144
- Organization12 DEDICATED INPUTS, 78 I/O
- Package CodeWPGA
- Package ShapeSQUARE
- Package StyleGRID ARRAY, WINDOW Meter
- Surface MountNO
- Terminal FormPIN/PEG
- Output FunctionMACROCELL
- DLA QualificationNot Qualified
- Temperature GradeMILITARY
- Terminal PositionPERPENDICULAR
- Additional Feature108 MACROCELLS; CONFIGURABLE I/O OPERATION-3.3V OR 5V; 3 EXTERNAL CLOCKS; 198 FLIP-FLOPS
- Number of I/O Lines78
- Number of Terminals144
- Terminal Pitch (mm)2.54
- Number of Macro Cells108
- Package Body MaterialCERAMIC, METAL-SEALED COFIRED
- In-System ProgrammableNO
- Propagation Delay (ns)45
- Seated Height-Max (mm)3.683
- Supply Voltage-Max (V)5.5
- Supply Voltage-Min (V)4.5
- Supply Voltage-Nom (V)5
- Programmable Logic TypeUV PLD
- Package Equivalence CodePGA144,15X15
- Clock Frequency-Max (MHz)35.7
- Moisture Sensitivity Level1
- Number of Dedicated Inputs12
- Operating Temperature-Max (Cel)125
- Operating Temperature-Min (Cel)-55
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XC73108-20PG144M