XC3042-70PG132M

Xilinx,Inc.

Xilinx,Inc. XC3042-70PG132M
  • ECCN
    3A001.a.2.c
  • ECCN Governance
    EAR
  • HTS Code
    8542.31.00.60
  • SB Code
    8542.31.00.60
  • Technology
    CMOS
  • Width (mm)
    37.084
  • Length (mm)
    37.084
  • JESD-30 Code
    S-CPGA-P132
  • Organization
    144 CLBS, 2000 GATES
  • Package Code
    PGA
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY Meter
  • Surface Mount
    NO
  • Terminal Form
    PIN/PEG
  • J-STD-609 Code
    e3
  • Number of CLBs
    144
  • Terminal Finish
    MATTE TIN
  • Number of Inputs
    96
  • DLA Qualification
    Not Qualified
  • Number of Outputs
    96
  • Temperature Grade
    MILITARY
  • Terminal Position
    PERPENDICULAR
  • Additional Feature
    480 FLIP-FLOPS; TYP. GATES = 2000-3000; POWER-DOWN SUPPLY CURRENT = 120UA
  • Number of Terminals
    132
  • Terminal Pitch (mm)
    2.54
  • Number of Logic Cells
    144
  • Package Body Material
    CERAMIC, METAL-SEALED COFIRED
  • Seated Height-Max (mm)
    3.9116
  • Supply Voltage-Max (V)
    5.5
  • Supply Voltage-Min (V)
    4.5
  • Supply Voltage-Nom (V)
    5
  • Programmable Logic Type
    FIELD PROGRAMMABLE GATE ARRAY
  • Package Equivalence Code
    PGA132,14X14
  • Clock Frequency-Max (MHz)
    70
  • Number of Equivalent Gates
    2000
  • Operating Temperature-Max (Cel)
    125
  • Operating Temperature-Min (Cel)
    -55
  • Combinatorial Delay of a CLB-Max (ns)
    9

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