XC2S50E-6FTGG256I

Xilinx,Inc.

Xilinx,Inc. XC2S50E-6FTGG256I
  • HTS Code
    8542.39.00.01
  • SB Code
    8542.31.00.60
  • Width (mm)
    17
  • Length (mm)
    17
  • JESD-30 Code
    S-PBGA-B256
  • Organization
    864 CLBS, 52000 GATES
  • Package Code
    FBGA
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY, FINE PITCH Meter
  • Surface Mount
    YES
  • Terminal Form
    B
  • J-STD-609 Code
    e1
  • Number of CLBs
    864
  • Terminal Finish
    TIN SILVER COPPER
  • Number of Inputs
    182
  • DLA Qualification
    Not Qualified
  • Number of Outputs
    182
  • Terminal Position
    BOTTOM
  • Additional Feature
    MAXIMUM USABLE GATES = 150000
  • Number of Terminals
    256
  • Terminal Pitch (mm)
    1
  • Package Body Material
    PLASTIC/EPOXY
  • Seated Height-Max (mm)
    1.55
  • Supply Voltage-Max (V)
    1.89
  • Supply Voltage-Min (V)
    1.71
  • Supply Voltage-Nom (V)
    1.8
  • Programmable Logic Type
    FIELD PROGRAMMABLE GATE ARRAY
  • Clock Frequency-Max (MHz)
    357
  • Number of Equivalent Gates
    52000
  • Operating Temperature-Max (Cel)
    100
  • Operating Temperature-Min (Cel)
    -40
  • Combinatorial Delay of a CLB-Max (ns)
    0.47

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