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XC2C512-10FT256I

Xilinx,Inc.

Xilinx,Inc. XC2C512-10FT256I
  • ECCN
    3A991.D
  • ECCN Governance
    EAR
  • HTS Code
    8542.39.00.01
  • SB Code
    8542.39.00.00
  • JTAG BST
    YES
  • Technology
    CMOS
  • Width (mm)
    17
  • Length (mm)
    17
  • Architecture
    PLA-TYPE
  • JESD-30 Code
    S-PBGA-B256
  • Organization
    0 DEDICATED INPUTS, 212 I/O
  • Package Code
    LBGA
  • Package Shape
    SQUARE
  • Package Style
    GRID ARRAY, LOW PROFILE Meter
  • Surface Mount
    YES
  • Terminal Form
    BALL
  • J-STD-609 Code
    e0
  • Output Function
    MACROCELL
  • Terminal Finish
    TIN LEAD
  • Number of Inputs
    212
  • DLA Qualification
    Not Qualified
  • Number of Outputs
    212
  • Temperature Grade
    INDUSTRIAL
  • Terminal Position
    BOTTOM
  • Additional Feature
    YES
  • Number of I/O Lines
    212
  • Number of Terminals
    256
  • Terminal Pitch (mm)
    1
  • Number of Macro Cells
    512
  • Package Body Material
    PLASTIC/EPOXY
  • In-System Programmable
    YES
  • Propagation Delay (ns)
    10
  • Seated Height-Max (mm)
    1.55
  • Supply Voltage-Max (V)
    1.9
  • Supply Voltage-Min (V)
    1.7
  • Supply Voltage-Nom (V)
    1.8
  • Programmable Logic Type
    FLASH PLD
  • Package Equivalence Code
    BGA256,16X16,40
  • Clock Frequency-Max (MHz)
    91
  • Moisture Sensitivity Level
    3
  • Number of Dedicated Inputs
    0
  • Peak Reflow Temperature (Cel)
    225
  • Operating Temperature-Max (Cel)
    85
  • Operating Temperature-Min (Cel)
    -40
  • Time@Peak Reflow Temperature-Max (s)
    30

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