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SM4J-67201AV-50SHXXX

MATRA MHS

MATRA MHS SM4J-67201AV-50SHXXX
  • ECCN
    EAR99
  • ECCN Governance
    EAR
  • HTS Code
    8542.32.00.71
  • SB Code
    8542.32.00.70
  • Technology
    CMOS
  • JESD-30 Code
    R-CQCC-N32
  • Memory Width
    9
  • Package Code
    QCCN
  • Output Enable
    NO
  • Package Shape
    RECTANGULAR
  • Package Style
    CHIP CARRIER Meter
  • Surface Mount
    YES
  • Terminal Form
    NO LEAD
  • Memory IC Type
    BI-DIRECTIONAL FIFO
  • Operating Mode
    ASYNCHRONOUS
  • Cycle Time (ns)
    65
  • Parallel/Serial
    PARALLEL
  • DLA Qualification
    Not Qualified
  • Temperature Grade
    MILITARY
  • Terminal Position
    QUAD
  • Additional Feature
    RETRANSMIT; 2V DATA RETENTION
  • Memory Organization
    512X9
  • Number of Functions
    1
  • Number of Terminals
    32
  • Access Time-Max (ns)
    50
  • Number of Words Code
    512
  • Memory Density (bits)
    4608
  • Package Body Material
    CERAMIC, METAL-SEALED COFIRED
  • Output Characteristics
    3-STATE
  • Supply Voltage-Max (V)
    5.5
  • Supply Voltage-Min (V)
    4.5
  • Supply Voltage-Nom (V)
    5
  • Number of Words (words)
    512
  • Supply Current-Max (mA)
    100
  • Operating Temperature-Max (Cel)
    125
  • Operating Temperature-Min (Cel)
    -55

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SM4J-67201AV-50SHXXX
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SM4J-67201AV-50SHXXX