Silicon Laboratories, Inc. SI53112-A03AGMR | 搜芯易Sourcengine

Silicon Laboratories, Inc. SI53112-A03AGMR

生命周期状态
Transferred
RoHS
符合RoHS标准
REACH
REACH compliant
说明
PLL Based Clock Driver, 53112 Series, 24 True Output(s), 0 Inverted Output(s)
类别
Semiconductors Logic ICs Clock Drivers PLL BASED CLOCK DRIVER

HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Family
53112
Width (mm)
9
Length (mm)
9
JESD-30 Code
S-XQCC-N64
Package Code
HVQCCN
Logic IC Type
PLL BASED CLOCK DRIVER
Package Shape
SQUARE
Package Style
CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE Meter
Surface Mount
YES
Terminal Form
NO LEAD
J-STD-609 Code
e3
Terminal Finish
MATTE TIN
Temperature Grade
INDUSTRIAL
Terminal Position
QUAD
Input Conditioning
DIFFERENTIAL MUX
Number of Functions
1
Number of Terminals
64
Terminal Pitch (mm)
0.5
Package Body Material
UNSPECIFIED
Number of True Outputs
24
Output Characteristics
3-STATE
Propagation Delay (ns)
4.5
Seated Height-Max (mm)
0.95
Supply Voltage-Max (V)
3.465
Supply Voltage-Min (V)
3.135
Supply Voltage-Nom (V)
3.3
Moisture Sensitivity Level
2
Number of Inverted Outputs
0
Peak Reflow Temperature (Cel)
260
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
-40
Same Edge Clock Skew Delay-Max (ns)
0.05
Time@Peak Reflow Temperature-Max (s)
40