SG5722885D8DRCL02
Smart Modular Technologies, Inc.
- 生命周期状态Discontinued
- RoHS符合RoHS标准
- 说明DDR1 DRAM Module, 128MX72, 0.7ns, CMOS, PDMA200
- 类别
- ECCNEAR99
- ECCN GovernanceEAR
- HTS Code8542.32.00.71
- SB Code8542.32.00.70
- I/O TypeCOMMON
- TechnologyCMOS
- Width (mm)5.9
- Access ModeFOUR BANK PAGE BURST
- Length (mm)67.6
- JESD-30 CodeR-PDMA-N200
- Memory Width72
- Package CodeDIMM
- Self RefreshYES
- Package ShapeRECTANGULAR
- Package StyleMICROELECTRONIC ASSEMBLY Meter
- Surface MountNO
- Terminal FormNO LEAD
- Memory IC TypeDDR1 DRAM MODULE
- Operating ModeSYNCHRONOUS
- Refresh Cycles8192
- Number of Ports1
- DLA QualificationNot Qualified
- Temperature GradeCOMMERCIAL
- Terminal PositionDUAL
- Additional FeatureWD-MAX
- Memory Organization128MX72
- Number of Functions1
- Number of Terminals200
- Terminal Pitch (mm)0.6
- Access Time-Max (ns)0.7
- Number of Words Code128M
- Memory Density (bits)9663676416
- Package Body MaterialPLASTIC/EPOXY
- Output Characteristics3-STATE
- Seated Height-Max (mm)31.9
- Supply Voltage-Max (V)2.7
- Supply Voltage-Min (V)2.3
- Supply Voltage-Nom (V)2.5
- Number of Words (words)134217728
- Sequential Burst Length2,4,8
- Standby Current-Max (A)0.624
- Supply Current-Max (mA)4620
- Interleaved Burst Length2,4,8
- Package Equivalence CodeDIMM200,24
- Clock Frequency-Max (MHz)166
- Operating Temperature-Max (Cel)70
- Operating Temperature-Min (Cel)0
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SG5722885D8DRCL02