PZ3960C7EB-S
Xilinx,Inc.
- 生命周期状态Discontinued
- 说明Loadable PLD, 9ns, 960-Cell, CMOS, PBGA492
- 类别
- ECCN3A991.d
- ECCN GovernanceEAR
- HTS Code8542.31.00.55
- SB Code8542.31.00.55
- JTAG BSTYES
- TechnologyCMOS
- Width (mm)35
- Length (mm)35
- JESD-30 CodeS-PBGA-B492
- Organization0 DEDICATED INPUTS, 384 I/O
- Package CodeBGA
- Package ShapeSQUARE
- Package StyleGRID ARRAY Meter
- Surface MountYES
- Terminal FormBALL
- J-STD-609 Codee0
- Packing MethodTRAY
- Output FunctionMACROCELL
- Terminal FinishTIN LEAD
- Number of Inputs384
- DLA QualificationNot Qualified
- Number of Outputs384
- Temperature GradeCOMMERCIAL
- Terminal PositionBOTTOM
- Additional FeatureNO
- Number of I/O Lines384
- Number of Terminals492
- Terminal Pitch (mm)1.27
- Number of Macro Cells960
- Package Body MaterialPLASTIC/EPOXY
- In-System ProgrammableNO
- Propagation Delay (ns)9
- Seated Height-Max (mm)2.54
- Supply Voltage-Max (V)3.63
- Supply Voltage-Min (V)2.97
- Supply Voltage-Nom (V)3.3
- Programmable Logic TypeLOADABLE PLD
- Package Equivalence CodeBGA492,26X26,50
- Clock Frequency-Max (MHz)100
- Number of Dedicated Inputs0
- Operating Temperature-Max (Cel)70
- Operating Temperature-Min (Cel)0
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