PLSI3256-70LG167
Lattice Semiconductor
- 生命周期状态Discontinued
- 说明EE PLD, 18ns, CMOS, CPGA167
- 类别
- HTS Code8542.39.00.01
- SB Code8542.31.00.55
- TechnologyCMOS
- Width (mm)44.45
- Length (mm)44.45
- JESD-30 CodeS-CPGA-P167
- Organization0 DEDICATED INPUTS, 128 I/O
- Package CodePGA
- Package ShapeSQUARE
- Package StyleGRID ARRAY Meter
- Surface MountNO
- Terminal FormPIN/PEG
- Output FunctionMACROCELL
- DLA QualificationNot Qualified
- Temperature GradeCOMMERCIAL
- Terminal PositionPERPENDICULAR
- Additional Feature32 TWIN GLBS; 5 EXTERNAL CLOCKS; SYNCHRONOUS & ASYNCHRONOUS CLOCKS
- Number of I/O Lines128
- Number of Terminals167
- Terminal Pitch (mm)2.54
- Package Body MaterialCERAMIC, METAL-SEALED COFIRED
- Propagation Delay (ns)18
- Seated Height-Max (mm)3.683
- Supply Voltage-Max (V)5.25
- Supply Voltage-Min (V)4.75
- Supply Voltage-Nom (V)5
- Programmable Logic TypeEE PLD
- Clock Frequency-Max (MHz)50
- Number of Dedicated Inputs0
- Operating Temperature-Max (Cel)70
- Operating Temperature-Min (Cel)0
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PLSI3256-70LG167