Lattice Semiconductor PLSI3256-70LG | 搜芯易Sourcengine

Lattice Semiconductor PLSI3256-70LG

生命周期状态
Discontinued
说明
EE PLD, 18ns, 256-Cell, CMOS, CPGA167
类别
Semiconductors Programmable Logic ICs Programmable Logic Devices EE PLD

HTS Code
8542.39.00.01
SB Code
8542.31.00.55

JTAG BST
NO
Technology
CMOS
Width (mm)
44.45
Length (mm)
44.45
JESD-30 Code
S-CPGA-P167
Organization
0 DEDICATED INPUTS, 128 I/O
Package Code
PGA
Package Shape
SQUARE
Package Style
GRID ARRAY Meter
Surface Mount
NO
Terminal Form
PIN/PEG
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
DLA Qualification
Not Qualified
Temperature Grade
COMMERCIAL
Terminal Position
PERPENDICULAR
Additional Feature
5 EXTERNAL CLOCKS
Number of I/O Lines
128
Number of Terminals
167
Terminal Pitch (mm)
2.54
Number of Macro Cells
256
Package Body Material
CERAMIC, METAL-SEALED COFIRED
In-System Programmable
NO
Propagation Delay (ns)
18
Supply Voltage-Max (V)
5.25
Supply Voltage-Min (V)
4.75
Supply Voltage-Nom (V)
5
Programmable Logic Type
EE PLD
Package Equivalence Code
PGA167,17X17
Clock Frequency-Max (MHz)
50
Number of Dedicated Inputs
0
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0