INTEGRATED CIRCUIT TECHNOLOGY CORP PEEL18CV8LP-15 | 搜芯易Sourcengine

INTEGRATED CIRCUIT TECHNOLOGY CORP PEEL18CV8LP-15

生命周期状态
Discontinued
说明
EE PLD, 15ns, PAL-Type, CMOS, PDIP20
类别
Semiconductors Programmable Logic ICs Programmable Logic Devices EE PLD

HTS Code
8542.39.00.01
SB Code
8542.31.00.55

Technology
CMOS
Width (mm)
7.62
Length (mm)
26.162
Architecture
PAL-TYPE
JESD-30 Code
R-PDIP-T20
Organization
9 DEDICATED INPUTS, 8 I/O
Package Code
DIP
Package Shape
RECTANGULAR
Package Style
IN-LINE Meter
Surface Mount
NO
Terminal Form
THROUGH-HOLE
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
Tin/Lead (Sn/Pb)
Number of Inputs
18
DLA Qualification
Not Qualified
Number of Outputs
8
Temperature Grade
COMMERCIAL
Terminal Position
DUAL
Additional Feature
8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Number of I/O Lines
8
Number of Terminals
20
Terminal Pitch (mm)
2.54
Package Body Material
PLASTIC/EPOXY
Propagation Delay (ns)
15
Supply Voltage-Max (V)
5.25
Supply Voltage-Min (V)
4.75
Supply Voltage-Nom (V)
5
Number of Product Terms
74
Programmable Logic Type
EE PLD
Package Equivalence Code
DIP20,.3
Clock Frequency-Max (MHz)
41.6
Number of Dedicated Inputs
9
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0