MC88920DWR2
Freescale Semiconductor, Inc.
- 生命周期状态Transferred
- 说明PLL Based Clock Driver, 88920 Series, 5 True Output(s), 1 Inverted Output(s), CMOS, PDSO20
- 类别
- HTS Code8542.39.00.01
- SB Code8542.39.00.00
- Family88920
- TechnologyCMOS
- Width (mm)7.5
- Length (mm)12.8
- JESD-30 CodeR-PDSO-G20
- Package CodeSOP
- Logic IC TypePLL BASED CLOCK DRIVER
- Package ShapeRECTANGULAR
- Package StyleSMALL OUTLINE Meter
- Surface MountYES
- Terminal FormGULL WING
- J-STD-609 Codee0
- fmax-Min (MHz)12.5
- Terminal FinishTin/Lead (Sn/Pb)
- DLA QualificationNot Qualified
- Temperature GradeCOMMERCIAL
- Terminal PositionDUAL
- Additional FeatureO/P FREQUENCY RATIOS ARE 1.0F/2.0F/4.0F; MEETS 68030 & 68040 SKEW REQUIREMENTS
- Input ConditioningSTANDARD
- Number of Functions1
- Number of Terminals20
- Terminal Pitch (mm)1.27
- Package Body MaterialPLASTIC/EPOXY
- Number of True Outputs5
- Propagation Delay (ns)3.25
- Seated Height-Max (mm)2.65
- Supply Voltage-Max (V)5.5
- Supply Voltage-Min (V)4.5
- Supply Voltage-Nom (V)5
- Package Equivalence CodeSOP20,.4
- Moisture Sensitivity Level1
- Number of Inverted Outputs1
- Peak Reflow Temperature (Cel)220
- Operating Temperature-Max (Cel)70
- Operating Temperature-Min (Cel)0
- Same Edge Clock Skew Delay-Max (ns)1
- Time@Peak Reflow Temperature-Max (s)30
MC88920DWR2有0家供应商货源可供购买或竞价
提交询价
您的询价单将直接发送给我们的销售专家: Pari
提交询价
MC88920DWR2