Samsung Semiconductor, Inc. M312L5128AU0-A2 | 搜芯易Sourcengine

Samsung Semiconductor, Inc. M312L5128AU0-A2

生命周期状态
Discontinued
RoHS
符合RoHS标准
说明
Cache DRAM Module, 512MX72, 0.75ns, CMOS, PDMA184
类别
Semiconductors Memory ICs DRAMs CACHE DRAM MODULE

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.32.00.36
SB Code
8542.32.00.23

I/O Type
COMMON
Technology
CMOS
JESD-30 Code
R-PDMA-N184
Memory Width
72
Organization
512MX72
Package Code
DIMM
JESD-609 Code
e3
Package Shape
RECTANGULAR
Package Style
MICROELECTRONIC ASSEMBLY Meter
Surface Mount
NO
Terminal Form
NO LEAD
Memory Density
38654705664 bit
Memory IC Type
CACHE DRAM MODULE
Refresh Cycles
8192
Terminal Pitch
1.27 mm
Access Time-Max
0.75 ns
Number of Words
536870912 words
Terminal Finish
MATTE TIN
Temperature Grade
COMMERCIAL
Terminal Position
DUAL
Supply Current-Max
8740 mA
Number of Terminals
184
Standby Current-Max
1.12 Amp
Number of Words Code
512M
Qualification Status
Not Qualified
Package Body Material
PLASTIC/EPOXY
Output Characteristics
3-STATE
Package Equivalence Code
DIMM184
Operating Temperature-Max
70 Cel
Operating Temperature-Min
0 Cel
Supply Voltage-Nom (Vsup)
2.5 V
Clock Frequency-Max (fCLK)
133 MHz
Moisture Sensitivity Level
1