Lattice Semiconductor LC4256V-75FN256AC | 搜芯易Sourcengine

Lattice Semiconductor LC4256V-75FN256AC

生命周期状态
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RoHS
符合RoHS标准
REACH
REACH compliant
说明
CPLD ispMACH® 4000V Family 256 Macro Cells 168MHz 3.3V 256-Pin FBGA
类别
Semiconductors Programmable Logic ICs Programmable Logic Devices EE PLD

HTS Code
8542.39.00.01
SB Code
8542.31.00.55

JTAG BST
YES
Width (mm)
17
Length (mm)
17
Architecture
PAD-TYPE
JESD-30 Code
S-PBGA-B256
Organization
4 DEDICATED INPUTS, 128 I/O
Package Code
BGA
Package Shape
SQUARE
Package Style
GRID ARRAY Meter
Surface Mount
YES
Terminal Form
BALL
J-STD-609 Code
e1
Output Function
MACROCELL
Terminal Finish
Tin/Silver/Copper (Sn/Ag/Cu)
Number of Inputs
132
DLA Qualification
Not Qualified
Number of Outputs
128
Terminal Position
BOTTOM
Number of I/O Lines
128
Number of Terminals
256
Terminal Pitch (mm)
1
Number of Macro Cells
256
Package Body Material
PLASTIC/EPOXY
In-System Programmable
YES
Propagation Delay (ns)
7.5
Seated Height-Max (mm)
2.1
Supply Voltage-Max (V)
3.6
Supply Voltage-Min (V)
3
Supply Voltage-Nom (V)
3.3
Number of Product Terms
83
Programmable Logic Type
EE PLD
Package Equivalence Code
BGA256,16X16,40
Clock Frequency-Max (MHz)
111
Moisture Sensitivity Level
3
Number of Dedicated Inputs
4
Peak Reflow Temperature (Cel)
250
Operating Temperature-Max (Cel)
90
Operating Temperature-Min (Cel)
0
Time@Peak Reflow Temperature-Max (s)
40