Samsung Semiconductor, Inc. K4T51043QB-GLCC | 搜芯易Sourcengine

Samsung Semiconductor, Inc. K4T51043QB-GLCC

生命周期状态
Active-Unconfirmed
REACH
REACH compliant
说明
DDR2 DRAM, 128MX4, 0.6ns, CMOS, PBGA60
类别
Semiconductors Memory ICs DRAMs DDR2 DRAM

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.32.00.28
SB Code
8542.32.00.15

I/O Type
COMMON
Technology
CMOS
JESD-30 Code
R-PBGA-B60
Memory Width
4
Organization
128MX4
Package Code
FBGA
JESD-609 Code
e0
Package Shape
RECTANGULAR
Package Style
GRID ARRAY, FINE PITCH Meter
Surface Mount
YES
Terminal Form
BALL
Memory Density
536870912 bit
Memory IC Type
DDR2 DRAM
Refresh Cycles
8192
Terminal Pitch
0.8 mm
Access Time-Max
0.6 ns
Number of Words
134217728 words
Terminal Finish
Tin/Lead (Sn/Pb)
Terminal Position
BOTTOM
Number of Terminals
60
Number of Words Code
128M
Qualification Status
Not Qualified
Package Body Material
PLASTIC/EPOXY
Output Characteristics
3-STATE
Sequential Burst Length
2,4
Interleaved Burst Length
4,8
Package Equivalence Code
BGA60,8X15,32
Supply Voltage-Nom (Vsup)
1.8 V
Clock Frequency-Max (fCLK)
200 MHz