Integrated Device Technology, Inc. IDT79R3721-25J | 搜芯易Sourcengine

Integrated Device Technology, Inc. IDT79R3721-25J

生命周期状态
Discontinued
说明
DRAM Controller, 4M X 4, CMOS, PQCC84
类别
Semiconductors UPs/uCs/Peripheral ICs Memory Controllers MEMORY CONTROLLER, DRAM

HTS Code
8542.31.00.01
SB Code
8542.31.00.30

Technology
CMOS
Width (mm)
29.2862
Length (mm)
29.2862
JESD-30 Code
S-PQCC-J84
Package Code
QCCJ
Boundary Scan
NO
Package Shape
SQUARE
Package Style
CHIP CARRIER Meter
Surface Mount
YES
Terminal Form
J BEND
J-STD-609 Code
e0
Low Power Mode
NO
Number of Banks
4
Terminal Finish
TIN LEAD
Address Bus Width
26
Bus Compatibility
R3051
DLA Qualification
Not Qualified
Temperature Grade
COMMERCIAL
Terminal Position
QUAD
Additional Feature
NON-INTERLEAVED/TWO-WAY INTERLEAVED; PAGE MODE OPERATION
Memory Organization
4M X 4
Number of Terminals
84
Terminal Pitch (mm)
1.27
Package Body Material
PLASTIC/EPOXY
Seated Height-Max (mm)
4.57
Supply Voltage-Max (V)
5.25
Supply Voltage-Min (V)
4.75
Supply Voltage-Nom (V)
5
External Data Bus Width
16
Supply Current-Max (mA)
200
Package Equivalence Code
LDCC84,1.2SQ
Clock Frequency-Max (MHz)
25
Moisture Sensitivity Level
1
uPs/uCs/Peripheral ICs Type
MEMORY CONTROLLER, DRAM
Peak Reflow Temperature (Cel)
225
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0
Time@Peak Reflow Temperature-Max (s)
30