Integrated Device Technology, Inc. ICS9DB102YGT | 搜芯易Sourcengine

Integrated Device Technology, Inc. ICS9DB102YGT

生命周期状态
Transferred
REACH
REACH compliant
说明
PLL Based Clock Driver, 9DB Series, 2 True Output(s), 0 Inverted Output(s), PDSO20
类别
Semiconductors Logic ICs Clock Drivers PLL BASED CLOCK DRIVER

HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Family
9DB
Width (mm)
4.4
Length (mm)
6.5
JESD-30 Code
R-PDSO-G20
Package Code
TSSOP
Logic IC Type
PLL BASED CLOCK DRIVER
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e0
Terminal Finish
TIN LEAD
DLA Qualification
Not Qualified
Temperature Grade
COMMERCIAL
Terminal Position
DUAL
Input Conditioning
DIFFERENTIAL
Number of Functions
1
Number of Terminals
20
Terminal Pitch (mm)
0.65
Package Body Material
PLASTIC/EPOXY
Number of True Outputs
2
Output Characteristics
3-STATE
Propagation Delay (ns)
0.185
Seated Height-Max (mm)
1.2
Supply Voltage-Max (V)
3.465
Supply Voltage-Min (V)
3.135
Supply Voltage-Nom (V)
3.3
Moisture Sensitivity Level
1
Number of Inverted Outputs
0
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0
Same Edge Clock Skew Delay-Max (ns)
0.025