SK Hynix HY5PS56821AFP-E3 | 搜芯易Sourcengine

SK Hynix HY5PS56821AFP-E3

生命周期状态
Active-Unconfirmed
RoHS
符合RoHS标准
REACH
REACH compliant
说明
DDR2 DRAM, 32MX8, 0.6ns, CMOS, PBGA60
类别
Semiconductors Memory ICs DRAMs DDR2 DRAM

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.32.00.24
SB Code
8542.32.00.15

I/O Type
COMMON
Technology
CMOS
JESD-30 Code
R-PBGA-B60
Memory Width
8
Package Code
FBGA
Package Shape
RECTANGULAR
Package Style
GRID ARRAY, FINE PITCH Meter
Surface Mount
YES
Terminal Form
BALL
Memory IC Type
DDR2 DRAM
Refresh Cycles
8192
DLA Qualification
Not Qualified
Temperature Grade
OTHER
Terminal Position
BOTTOM
Memory Organization
32MX8
Number of Terminals
60
Terminal Pitch (mm)
0.8
Access Time-Max (ns)
0.6
Number of Words Code
32M
Memory Density (bits)
268435456
Package Body Material
PLASTIC/EPOXY
Output Characteristics
3-STATE
Supply Voltage-Nom (V)
1.8
Number of Words (words)
33554432
Sequential Burst Length
4,8
Interleaved Burst Length
4,8
Package Equivalence Code
BGA60,9X11,32
Clock Frequency-Max (MHz)
200
Operating Temperature-Max (Cel)
95
Operating Temperature-Min (Cel)
0