SK Hynix HMP512F7FFP8C-Y5D3 | 搜芯易Sourcengine

SK Hynix HMP512F7FFP8C-Y5D3

生命周期状态
Discontinued
RoHS
符合RoHS标准
REACH
REACH compliant
说明
DDR2 DRAM Module, 128MX72, CMOS
类别
Semiconductors Memory ICs DRAMs DDR2 DRAM MODULE

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.32.00.36
SB Code
8542.32.00.23

Technology
CMOS
Access Mode
DUAL BANK PAGE BURST
JESD-30 Code
R-XDMA-N240
Memory Width
72
Package Code
DIMM
Self Refresh
YES
Package Shape
RECTANGULAR
Package Style
MICROELECTRONIC ASSEMBLY Meter
Surface Mount
NO
Terminal Form
NO LEAD
Memory IC Type
DDR2 DRAM MODULE
Operating Mode
SYNCHRONOUS
Refresh Cycles
8192
Number of Ports
1
DLA Qualification
Not Qualified
Temperature Grade
OTHER
Terminal Position
DUAL
Additional Feature
AUTO/SELF REFRESH
Memory Organization
128MX72
Number of Functions
1
Number of Terminals
240
Terminal Pitch (mm)
1
Number of Words Code
128M
Memory Density (bits)
9663676416
Package Body Material
UNSPECIFIED
Supply Voltage-Max (V)
1.575
Supply Voltage-Min (V)
1.455
Supply Voltage-Nom (V)
1.5
Number of Words (words)
134217728
Package Equivalence Code
DIMM240,40
Peak Reflow Temperature (Cel)
260
Operating Temperature-Max (Cel)
95
Operating Temperature-Min (Cel)
0
Time@Peak Reflow Temperature-Max (s)
20