HM511002AP-12
Hitachi, Ltd.
- 生命周期状态Discontinued
- 说明Static Column DRAM, 1MX1, 120ns, CMOS, PDIP18
- 类别
- ECCNEAR99
- ECCN GovernanceEAR
- HTS Code8542.32.00.02
- SB Code8542.32.00.15
- Width7.62 mm
- Length22.26 mm
- I/O TypeSEPARATE
- TechnologyCMOS
- Access ModeSTATIC COLUMN
- JESD-30 CodeR-PDIP-T18
- Memory Width1
- Organization1MX1
- Package CodeDIP
- JESD-609 Codee0
- Package ShapeRECTANGULAR
- Package StyleIN-LINE Meter
- Surface MountNO
- Terminal FormTHROUGH-HOLE
- Memory Density1048576 bit
- Memory IC TypeSTATIC COLUMN DRAM
- Operating ModeASYNCHRONOUS
- Refresh Cycles512
- Terminal Pitch2.54 mm
- Access Time-Max120 ns
- Number of Ports1
- Number of Words1048576 words
- Terminal FinishTIN LEAD
- Seated Height-Max5.08 mm
- Temperature GradeCOMMERCIAL
- Terminal PositionDUAL
- Additional FeatureRAS ONLY/CAS BEFORE RAS REFRESH
- Supply Current-Max50 mA
- Number of Functions1
- Number of Terminals18
- Standby Current-Max0.001 Amp
- Number of Words Code1M
- Qualification StatusNot Qualified
- Package Body MaterialPLASTIC/EPOXY
- Output Characteristics3-STATE
- Package Equivalence CodeDIP18,.3
- Operating Temperature-Max70 Cel
- Operating Temperature-Min0 Cel
- Supply Voltage-Max (Vsup)5.5 V
- Supply Voltage-Min (Vsup)4.5 V
- Supply Voltage-Nom (Vsup)5 V
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HM511002AP-12