Lattice Semiconductor GAL18V10-20LP | 搜芯易Sourcengine

Lattice Semiconductor GAL18V10-20LP

生命周期状态
Discontinued
说明
EE PLD, 20ns, PAL-Type, CMOS, PDIP20
类别
Semiconductors Programmable Logic ICs Programmable Logic Devices EE PLD

HTS Code
8542.39.00.01
SB Code
8542.31.00.55

Technology
CMOS
Width (mm)
7.62
Length (mm)
26.125
Architecture
PAL-TYPE
JESD-30 Code
R-PDIP-T20
Organization
7 DEDICATED INPUTS, 10 I/O
Package Code
DIP
Package Shape
RECTANGULAR
Package Style
IN-LINE Meter
Surface Mount
NO
Terminal Form
THROUGH-HOLE
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
Number of Inputs
18
DLA Qualification
Not Qualified
Number of Outputs
10
Temperature Grade
COMMERCIAL EXTENDED
Terminal Position
DUAL
Additional Feature
REGISTER PRELOAD; POWER-UP RESET
Number of I/O Lines
10
Number of Terminals
20
Terminal Pitch (mm)
2.54
Package Body Material
PLASTIC/EPOXY
Propagation Delay (ns)
20
Seated Height-Max (mm)
4.57
Supply Voltage-Max (V)
5.25
Supply Voltage-Min (V)
4.75
Supply Voltage-Nom (V)
5
Number of Product Terms
96
Programmable Logic Type
EE PLD
Package Equivalence Code
DIP20,.3
Clock Frequency-Max (MHz)
41.6
Number of Dedicated Inputs
7
Operating Temperature-Max (Cel)
75
Operating Temperature-Min (Cel)
0