ALTERA CORP EPM9560RC240-15 | 搜芯易Sourcengine

ALTERA CORP EPM9560RC240-15

生命周期状态
Transferred
说明
CPLD - Complex Programmable Logic Devices CPLD - MAX 9000 560 Macro 191 IOs
类别
Semiconductors Programmable Logic ICs Programmable Logic Devices EE PLD

HTS Code
8542.39.00.01
SB Code
8542.31.00.55

JTAG BST
YES
Technology
CMOS
Width (mm)
32
Length (mm)
32
JESD-30 Code
S-PQFP-G240
Organization
0 DEDICATED INPUTS, 191 I/O
Package Code
FQFP
Package Shape
SQUARE
Package Style
FLATPACK, FINE PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
DLA Qualification
Not Qualified
Temperature Grade
COMMERCIAL
Terminal Position
QUAD
Additional Feature
772 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
Number of I/O Lines
191
Number of Terminals
240
Terminal Pitch (mm)
0.5
Number of Macro Cells
560
Package Body Material
PLASTIC/EPOXY
In-System Programmable
YES
Propagation Delay (ns)
16.6
Seated Height-Max (mm)
4.1
Supply Voltage-Max (V)
5.25
Supply Voltage-Min (V)
4.75
Supply Voltage-Nom (V)
5
Programmable Logic Type
EE PLD
Package Equivalence Code
HQFP240,1.37SQ,20
Clock Frequency-Max (MHz)
117.6
Moisture Sensitivity Level
3
Number of Dedicated Inputs
0
Peak Reflow Temperature (Cel)
220
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0
Time@Peak Reflow Temperature-Max (s)
20