ALTERA CORP EPM7256EGC192-12P | 搜芯易Sourcengine

ALTERA CORP EPM7256EGC192-12P

生命周期状态
Discontinued
说明
EE PLD, 12ns, 256-Cell, CMOS, CPGA192
类别
Semiconductors Programmable Logic ICs Programmable Logic Devices EE PLD

HTS Code
8542.39.00.01
SB Code
8542.31.00.55

JTAG BST
NO
Technology
CMOS
Width (mm)
45.15
Length (mm)
45.15
JESD-30 Code
S-CPGA-P192
Organization
0 DEDICATED INPUTS, 160 I/O
Package Code
PGA
Package Shape
SQUARE
Package Style
GRID ARRAY Meter
Surface Mount
NO
Terminal Form
PIN/PEG
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
Number of Inputs
160
DLA Qualification
Not Qualified
Number of Outputs
160
Temperature Grade
COMMERCIAL
Terminal Position
PERPENDICULAR
Additional Feature
CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
Number of I/O Lines
160
Number of Terminals
192
Terminal Pitch (mm)
2.54
Number of Macro Cells
256
Package Body Material
CERAMIC, METAL-SEALED COFIRED
In-System Programmable
NO
Propagation Delay (ns)
12
Seated Height-Max (mm)
5.43
Supply Voltage-Max (V)
5.25
Supply Voltage-Min (V)
4.75
Supply Voltage-Nom (V)
5
Programmable Logic Type
EE PLD
Package Equivalence Code
PGA192M,17X17
Clock Frequency-Max (MHz)
90.9
Moisture Sensitivity Level
1
Number of Dedicated Inputs
0
Peak Reflow Temperature (Cel)
220
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0