EPM5128GI-2
ALTERA CORP
- 生命周期状态Transferred
- 说明UV PLD, 45ns, 128-Cell, CMOS, CPGA68
- 类别
- HTS Code8542.39.00.01
- SB Code8542.31.00.55
- JTAG BSTNO
- TechnologyCMOS
- JESD-30 CodeS-CPGA-P68
- Organization7 DEDICATED INPUTS, 52 I/O
- Package CodePGA
- Package ShapeSQUARE
- Package StyleGRID ARRAY Meter
- Surface MountNO
- Terminal FormPIN/PEG
- J-STD-609 Codee0
- Output FunctionMACROCELL
- Terminal FinishTIN LEAD
- DLA QualificationNot Qualified
- Temperature GradeINDUSTRIAL
- Terminal PositionPERPENDICULAR
- Additional FeatureLABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
- Number of I/O Lines52
- Number of Terminals68
- Terminal Pitch (mm)2.54
- Number of Macro Cells128
- Package Body MaterialCERAMIC, METAL-SEALED COFIRED
- In-System ProgrammableNO
- Propagation Delay (ns)45
- Supply Voltage-Max (V)5.5
- Supply Voltage-Min (V)4.5
- Supply Voltage-Nom (V)5
- Programmable Logic TypeUV PLD
- Package Equivalence CodePGA68,11X11
- Clock Frequency-Max (MHz)40
- Moisture Sensitivity Level1
- Number of Dedicated Inputs7
- Peak Reflow Temperature (Cel)220
- Operating Temperature-Max (Cel)85
- Operating Temperature-Min (Cel)-40
EPM5128GI-2有0家供应商货源可供购买或竞价
提交询价
您的询价单将直接发送给我们的销售专家: Pari
提交询价
EPM5128GI-2