ALTERA CORP EP20K60EFC144-3 | 搜芯易Sourcengine

ALTERA CORP EP20K60EFC144-3

生命周期状态
Transferred
说明
Loadable PLD, 3.56ns, CMOS, PBGA144
类别
Semiconductors Programmable Logic ICs Programmable Logic Devices LOADABLE PLD

HTS Code
8542.39.00.01
SB Code
8542.31.00.55

Technology
CMOS
Width (mm)
13
Length (mm)
13
JESD-30 Code
S-PBGA-B144
Organization
4 DEDICATED INPUTS, 93 I/O
Package Code
LBGA
Package Shape
SQUARE
Package Style
GRID ARRAY, LOW PROFILE Meter
Surface Mount
YES
Terminal Form
BALL
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
Number of Inputs
85
DLA Qualification
Not Qualified
Number of Outputs
85
Temperature Grade
OTHER
Terminal Position
BOTTOM
Number of I/O Lines
93
Number of Terminals
144
Terminal Pitch (mm)
1
Number of Logic Cells
2560
Package Body Material
PLASTIC/EPOXY
Propagation Delay (ns)
3.56
Seated Height-Max (mm)
1.7
Supply Voltage-Max (V)
1.89
Supply Voltage-Min (V)
1.71
Supply Voltage-Nom (V)
1.8
Programmable Logic Type
LOADABLE PLD
Package Equivalence Code
BGA144,12X12,40
Clock Frequency-Max (MHz)
160
Moisture Sensitivity Level
3
Number of Dedicated Inputs
4
Peak Reflow Temperature (Cel)
235
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
0
Time@Peak Reflow Temperature-Max (s)
20