ALTERA CORP EP20K400GI655-1 | 搜芯易Sourcengine

ALTERA CORP EP20K400GI655-1

生命周期状态
Discontinued
REACH
REACH compliant
说明
Loadable PLD, 2.5ns, CMOS, CPGA655
类别
Semiconductors Programmable Logic ICs Programmable Logic Devices LOADABLE PLD

ECCN
3A991.d
ECCN Governance
EAR
HTS Code
8542.31.00.55
SB Code
8542.31.00.55

Technology
CMOS
Width (mm)
62.484
Length (mm)
62.484
JESD-30 Code
S-CPGA-P655
Organization
4 DEDICATED INPUTS, 502 I/O
Package Code
IPGA
Package Shape
SQUARE
Package Style
GRID ARRAY, INTERSTITIAL PITCH Meter
Surface Mount
NO
Terminal Form
PIN/PEG
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
Number of Inputs
496
DLA Qualification
Not Qualified
Number of Outputs
496
Terminal Position
PERPENDICULAR
Number of I/O Lines
502
Number of Terminals
655
Terminal Pitch (mm)
2.54
Number of Logic Cells
16640
Package Body Material
CERAMIC, METAL-SEALED COFIRED
Propagation Delay (ns)
2.5
Seated Height-Max (mm)
4.08
Supply Voltage-Max (V)
2.625
Supply Voltage-Min (V)
2.375
Supply Voltage-Nom (V)
2.5
Programmable Logic Type
LOADABLE PLD
Package Equivalence Code
SPGA655,47X47
Clock Frequency-Max (MHz)
5000
Moisture Sensitivity Level
1
Number of Dedicated Inputs
4
Peak Reflow Temperature (Cel)
220
Operating Temperature-Max (Cel)
100
Operating Temperature-Min (Cel)
-40