ALTERA CORP EP20K400FI672-3 | 搜芯易Sourcengine

ALTERA CORP EP20K400FI672-3

生命周期状态
Discontinued
REACH
REACH compliant
说明
Loadable PLD, 3.6ns, CMOS, PBGA672
类别
Semiconductors Programmable Logic ICs Programmable Logic Devices LOADABLE PLD

ECCN
3A991.d
ECCN Governance
EAR
HTS Code
8542.31.00.55
SB Code
8542.31.00.55

Technology
CMOS
Width (mm)
27
Length (mm)
27
JESD-30 Code
S-PBGA-B672
Organization
4 DEDICATED INPUTS, 502 I/O
Package Code
BGA
Package Shape
SQUARE
Package Style
GRID ARRAY Meter
Surface Mount
YES
Terminal Form
BALL
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
Number of Inputs
496
DLA Qualification
Not Qualified
Number of Outputs
496
Terminal Position
BOTTOM
Number of I/O Lines
502
Number of Terminals
672
Terminal Pitch (mm)
1
Number of Logic Cells
16640
Package Body Material
PLASTIC/EPOXY
Propagation Delay (ns)
3.6
Seated Height-Max (mm)
2.1
Supply Voltage-Max (V)
2.625
Supply Voltage-Min (V)
2.375
Supply Voltage-Nom (V)
2.5
Programmable Logic Type
LOADABLE PLD
Package Equivalence Code
BGA672,26X26,40
Clock Frequency-Max (MHz)
833
Moisture Sensitivity Level
3
Number of Dedicated Inputs
4
Peak Reflow Temperature (Cel)
220
Operating Temperature-Max (Cel)
100
Operating Temperature-Min (Cel)
-40