ALTERA CORP EP20K160EQC208-2 | 搜芯易Sourcengine

ALTERA CORP EP20K160EQC208-2

生命周期状态
Transferred
说明
Loadable PLD, 1.93ns, CMOS, PQFP208
类别
Semiconductors Programmable Logic ICs Programmable Logic Devices LOADABLE PLD

HTS Code
8542.39.00.01
SB Code
8542.31.00.55

Technology
CMOS
Width (mm)
28
Length (mm)
28
JESD-30 Code
S-PQFP-G208
Organization
4 DEDICATED INPUTS, 143 I/O
Package Code
FQFP
Package Shape
SQUARE
Package Style
FLATPACK, FINE PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
Number of Inputs
135
DLA Qualification
Not Qualified
Number of Outputs
135
Temperature Grade
OTHER
Terminal Position
QUAD
Number of I/O Lines
143
Number of Terminals
208
Terminal Pitch (mm)
0.5
Number of Logic Cells
6400
Package Body Material
PLASTIC/EPOXY
Propagation Delay (ns)
1.93
Seated Height-Max (mm)
4.1
Supply Voltage-Max (V)
1.89
Supply Voltage-Min (V)
1.71
Supply Voltage-Nom (V)
1.8
Programmable Logic Type
LOADABLE PLD
Package Equivalence Code
QFP208,1.2SQ,20
Clock Frequency-Max (MHz)
160
Moisture Sensitivity Level
3
Number of Dedicated Inputs
4
Peak Reflow Temperature (Cel)
220
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
0
Time@Peak Reflow Temperature-Max (s)
20