ALTERA CORP EP1810GC68-35 | 搜芯易Sourcengine

ALTERA CORP EP1810GC68-35

生命周期状态
Discontinued
REACH
REACH compliant
说明
UV PLD, 40ns, 48-Cell, CMOS, CPGA68
类别
Semiconductors Programmable Logic ICs Programmable Logic Devices UV PLD

HTS Code
8542.39.00.01
SB Code
8542.31.00.55

JTAG BST
NO
Technology
CMOS
Width (mm)
27.94
Length (mm)
27.94
JESD-30 Code
S-CPGA-P68
Organization
12 DEDICATED INPUTS, 48 I/O
Package Code
WPGA
Package Shape
SQUARE
Package Style
GRID ARRAY, WINDOW Meter
Surface Mount
NO
Terminal Form
PIN/PEG
J-STD-609 Code
e0
Output Function
MACROCELL
Terminal Finish
TIN LEAD
Number of Inputs
60
DLA Qualification
Not Qualified
Number of Outputs
48
Temperature Grade
COMMERCIAL
Terminal Position
PERPENDICULAR
Additional Feature
48 MACROCELLS; SHARED INPUT/CLOCK
Number of I/O Lines
48
Number of Terminals
68
Terminal Pitch (mm)
2.54
Number of Macro Cells
48
Package Body Material
CERAMIC, METAL-SEALED COFIRED
In-System Programmable
NO
Propagation Delay (ns)
40
Seated Height-Max (mm)
4.96
Supply Voltage-Max (V)
5.25
Supply Voltage-Min (V)
4.75
Supply Voltage-Nom (V)
5
Programmable Logic Type
UV PLD
Package Equivalence Code
PGA68,11X11
Clock Frequency-Max (MHz)
40
Moisture Sensitivity Level
1
Number of Dedicated Inputs
12
Peak Reflow Temperature (Cel)
220
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0