DPAC TECHNOLOGIES CORP DPSD128MX8XKY5-DP-XXP12 | 搜芯易Sourcengine

DPAC TECHNOLOGIES CORP DPSD128MX8XKY5-DP-XXP12

生命周期状态
Discontinued
说明
Synchronous DRAM Module, 128MX8, CMOS, PDSO54
类别
Semiconductors Memory ICs DRAMs SYNCHRONOUS DRAM MODULE

ECCN
EAR99
ECCN Governance
EAR
HTS Code
8542.32.00.32
SB Code
8542.32.00.15

Technology
CMOS
Access Mode
FOUR BANK PAGE BURST
JESD-30 Code
R-PDSO-G54
Memory Width
8
Organization
128MX8
Package Code
ATSOP
Self Refresh
YES
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE, PIGGYBACK, THIN PROFILE Meter
Surface Mount
YES
Terminal Form
GULL WING
Memory Density
1073741824 bit
Memory IC Type
SYNCHRONOUS DRAM MODULE
Operating Mode
SYNCHRONOUS
Terminal Pitch
0.8 mm
Number of Ports
1
Number of Words
134217728 words
Seated Height-Max
2.59 mm
Terminal Position
DUAL
Additional Feature
AUTO/SELF REFRESH
Number of Functions
1
Number of Terminals
54
Number of Words Code
128M
Qualification Status
Not Qualified
Package Body Material
PLASTIC/EPOXY
Supply Voltage-Nom (Vsup)
3.3 V