INTEGRATED CIRCUIT SYSTEMS INC AV9112F-17LF | 搜芯易Sourcengine

INTEGRATED CIRCUIT SYSTEMS INC AV9112F-17LF

生命周期状态
Transferred
说明
PLL Based Clock Driver, 91 Series, 9 True Output(s), 0 Inverted Output(s), PDSO16
类别
Semiconductors Logic ICs Clock Drivers PLL BASED CLOCK DRIVER

HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Family
91
Width (mm)
3.9116
Length (mm)
4.9
JESD-30 Code
R-PDSO-G16
Package Code
SSOP
Logic IC Type
PLL BASED CLOCK DRIVER
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE, SHRINK PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e3
fmax-Min (MHz)
133
Terminal Finish
MATTE TIN
DLA Qualification
Not Qualified
Temperature Grade
COMMERCIAL
Terminal Position
DUAL
Additional Feature
IT CAN ALSO OPERATE FROM 4.5V TO 5.5V
Input Conditioning
STANDARD
Number of Functions
1
Number of Terminals
16
Terminal Pitch (mm)
0.635
Package Body Material
PLASTIC/EPOXY
Number of True Outputs
9
Output Characteristics
3-STATE
Seated Height-Max (mm)
1.75
Supply Voltage-Max (V)
3.63
Supply Voltage-Min (V)
2.97
Supply Voltage-Nom (V)
3.3
Package Equivalence Code
SSOP16,.25
Number of Inverted Outputs
0
Peak Reflow Temperature (Cel)
NOT SPECIFIED
Operating Temperature-Max (Cel)
70
Operating Temperature-Min (Cel)
0
Same Edge Clock Skew Delay-Max (ns)
0.25
Time@Peak Reflow Temperature-Max (s)
NOT SPECIFIED