Integrated Device Technology, Inc. 74LVC112AQ | 搜芯易Sourcengine

Integrated Device Technology, Inc. 74LVC112AQ

生命周期状态
Transferred
说明
QSOP 4.90x3.80x1.47 mm 0.64mm Pitch
类别
Semiconductors Logic ICs FF/Latches J-K FLIP-FLOP

HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Technology
CMOS
JESD-30 Code
R-PDSO-G16
Package Code
SSOP
Trigger Type
NEGATIVE EDGE
Logic IC Type
J-K FLIP-FLOP
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE, SHRINK PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e0
Terminal Finish
TIN LEAD
DLA Qualification
Not Qualified
Temperature Grade
INDUSTRIAL
Terminal Position
DUAL
Number of Functions
2
Number of Terminals
16
Terminal Pitch (mm)
0.635
Load Capacitance (pF)
50
Package Body Material
PLASTIC/EPOXY
Supply Voltage-Nom (V)
3.3
Package Equivalence Code
SSOP16,.25
Frequency-Max@Nom-Sup (Hz)
150000000
Moisture Sensitivity Level
1
Output Low Current-Max (mA)
24
Peak Reflow Temperature (Cel)
240
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
-40
Propagation Delay-Max@Nom-Sup (ns)
5.9
Time@Peak Reflow Temperature-Max (s)
20