PHILIPS SEMICONDUCTORS 74LV107PW-T | 搜芯易Sourcengine

PHILIPS SEMICONDUCTORS 74LV107PW-T

生命周期状态
Transferred
说明
J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, PDSO14
类别
Semiconductors Logic ICs FF/Latches J-K FLIP-FLOP

HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Technology
CMOS
JESD-30 Code
R-PDSO-G14
Package Code
TSSOP
Trigger Type
NEGATIVE EDGE
Logic IC Type
J-K FLIP-FLOP
Package Shape
RECTANGULAR
Package Style
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Meter
Surface Mount
YES
Terminal Form
GULL WING
J-STD-609 Code
e0
Packing Method
TR
Terminal Finish
Tin/Lead (Sn/Pb)
DLA Qualification
Not Qualified
Temperature Grade
AUTOMOTIVE
Terminal Position
DUAL
Number of Functions
2
Number of Terminals
14
Terminal Pitch (mm)
0.635
Load Capacitance (pF)
50
Package Body Material
PLASTIC/EPOXY
Supply Voltage-Nom (V)
3.3
Package Equivalence Code
TSSOP14,.25
Frequency-Max@Nom-Sup (Hz)
20000000
Output Low Current-Max (mA)
6
Operating Temperature-Max (Cel)
125
Operating Temperature-Min (Cel)
-40
Propagation Delay-Max@Nom-Sup (ns)
33