PHILIPS SEMICONDUCTORS 100117F | 搜芯易Sourcengine

PHILIPS SEMICONDUCTORS 100117F

生命周期状态
Transferred
说明
OR-AND/OR-AND-Invert Gate, ECL, CDIP24
类别
Semiconductors Logic ICs Gates OR-AND/OR-AND-INVERT GATE

HTS Code
8542.39.00.01
SB Code
8542.39.00.00

Technology
ECL
JESD-30 Code
R-XDIP-T24
Package Code
DIP
Logic IC Type
OR-AND/OR-AND-INVERT GATE
Package Shape
RECTANGULAR
Package Style
IN-LINE Meter
Surface Mount
NO
Terminal Form
THROUGH-HOLE
J-STD-609 Code
e0
Schmitt Trigger
NO
Terminal Finish
Tin/Lead (Sn/Pb)
DLA Qualification
Not Qualified
Temperature Grade
OTHER
Terminal Position
DUAL
Number of Terminals
24
Terminal Pitch (mm)
2.54
Package Body Material
CERAMIC
Supply Current-Max (mA)
79
Package Equivalence Code
DIP24,.4
Operating Temperature-Max (Cel)
85
Operating Temperature-Min (Cel)
0
Propagation Delay-Max@Nom-Sup (ns)
2.6